Accelerate modular, multi-tool design workflows

Overview

Infosys Semiconductor practice offers silicon design services to chip manufacturers and fabless enterprises, across hard and soft IP cores as well as functionalities. Our service portfolio spans front-end RTL design, SoC integration of multi-million gate IPs, FPGA and system architecture design, ASIC and IP prototyping with FPGA, physical design (RTL - GDSII), and pre-silicon and post-silicon validation.

Our team has robust capabilities in electronic design automation (EDA) flows to address dynamics such as miniaturization, functional density, power consumption, performance, reliability, and cost. It also enables us to design bespoke chips with robust routing and tracking capabilities. Our IC designers achieve first-time right design by capitalizing on rich experience in silicon compilers, layout editors and digital methodologies.

Infosys combines UVM-based functional and formal techniques and gate-level simulation of IP and SoC designs with workflow automation to ensure design accuracy. Our chip verification strategy capitalizes on power-aware simulation as well as static and dynamic checking. Our DFT approach optimizes IC test coverage, enabling functional bugs to be identified and resolved early in the design cycle. DFT flow optimization for Scan, OCC, Compression, ATPG, MBIST, and JTAG implementation as well as simulation boosts quality. Moreover, automated design processes and efficient functional verification of electronic systems drive flawless tapeout.

In addition, we integrate CAD and CAM services with product data management (PDM). CAx-PDM integration centralizes design documentation, which enhances visibility into design revisions, ensures traceability, and facilitates information sharing among engineering, production and procurement teams.